SystemVerilog allows reading parameter from interface

Question

I'm a little confused as to whether it is legal, in terms of standards, to read a parameter from an interface.

In this way

interface foo_if #(parameter BAR=5)(); ... logic [BAR-1:0] data; modport slave(input data, ...); endinterface module foobar(foo_if.slave s); ... logic [s.BAR-1:0] bar; logic [$bits(s.data)-1:0] m_data; ... endmodule 

I have a problem where the main developer of the synthesis tool cannot handle this. And they explicitly tell you in the help message that it is not allowed to use $ bits () with a member of the interface.

However, a simulation tool from another manufacturer does an excellent job of this, as does another synthesis tool.

However, in SystemVerilog for design S. Sutherland et al. it says:

Since the design hierarchy is not yet fully resolved during development, it is illegal to assign a parameter, specparam or localparam constants - a value obtained from other sources in the design hierarchy

However, if I am not allowed to use parameters from interfaces, this really distorts the usefulness of the interfaces.

The SystemVerilog 1800-2012 standard, on the other hand, indicates:

25.10 Access to interface objects

Access to objects declared in the interface should be accessible by a hierarchical name, regardless of whether the interface is also accessed through a port or through a virtual interface and regardless of the presence of any declared mods in this interface. The modport can be used to restrict access to objects declared in the interface referenced through the port or virtual interface, explicitly listing the available objects in the mod. However, objects that are unacceptable for the moport must remain accessible.

Answer 1

The problem here is not access, but permitted in places where constant expressions are required. LRM is not very clear that interface port links are not considered hierarchical links. But the tool does not complain about s.BAR , it complains about s.data , which is a variable, not a parameter. Generally, you cannot use variables in constant expressions, but LRM 20.6.2 says

The $ bits function can be used as a design-time constant when used for fixed-size data types; therefore, it can be used to declare other types of data, variables, or networks.

So $ bits (s.data) should be considered as an expression of the parameter.

By the way, you should use the latest freely available LRM IEEE 1800-2012 .