The difference between behavioral, RTL and gate level

Question

I am trying to fully understand the differences between the levels of abstraction Verilog, I get a description of each level, but I still can not get it in the game.

In this case, I will insert some Verilog codes and what I think of them:

• The following code is at the behavioral level.

  always @ (a or b or sel) begin y = 0; if (sel == 0) begin y = a; end else begin y = b; end end 

• This (just an example) is at the gate level

   module test(clk, ready, next, Q); input clk, enable, next; output Q; \**SEQGEN** reg_1 (.clear(1'b0), .next_state(next), .clocked_on(clk), .Q(Q), .synch_enable(enable) ); endmodule 

• I don’t know if this code is in RTL or Gate Level (I expect the always keyword will do it RTL, not Gate Level)

   module dff_from_nand(); wire Q,Q_BAR; reg D,CLK; nand U1 (X,D,CLK) ; nand U2 (Y,X,CLK) ; nand U3 (Q,Q_BAR,X); nand U4 (Q_BAR,Q,Y); // Testbench of above code initial begin $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR); CLK = 0; D = 0; #3 D = 1; #3 D = 0; #3 $finish; end always #2 CLK = ~CLK; endmodule 

I already know that initial begin and end not synthesized and are simply used for testing. I now have 2 questions

• Third (and second) RTL or Gate-Leve code? What would be a good example of RTL code? I found this sample RTL code , but is it really RTL? For me it looks like a behavioral level.

• What does the Verilog netlist mean? Is it the same as the gate level, or the definition of the context base?

I am confused because on some websites I don’t know if they say: “This is Verilog code that uses logical gates” or “this is Verilog code at the gate level”

I will be very happy if someone who wants to explain more detailed information about this topic :)

Answer 1

RTL : Register-Transfer-Level function, an abstraction written using always and assign blocks, which can be synthesized (can be translated to the gate level). Pure RTL does not create submodules. RTL may contain submodules to guide the synthesizer. Structural RTL (still called RTL) is a module that contains other RTL modules. Example: FSM (state machine)

 always @* begin next_state = state; if (count>0) next_count = count - 1; case (state) IDLE : if(do_start) begin next_state = START; next_count = 2; end START : if (do_wait) begin next_count = count; end else if (count==0) begin next_state = RUN; next_count = count_from_input; end RUN : if (do_stop) begin next_state = IDLE; end if (do_wait) begin next_count = count; end else if (count==0) begin next_state = IDLE; end endcase end always @(posedge clk, negedge rst_n) begin if (!rst_n) begin count <= 0; state <= IDLE; end else begin count <= next_count; state <= next_state; end end 

Behavioral : mimics the desired hardware functionality, but is not necessarily synthesized. There are no strict rules if the code generates the desired behavior. The guiding principle is to keep it simple and readable. Behavioral are often used to represent the analog block, place owner code (RTL / gates are not ready), and testbench code. Example: clock generator, delay cells.

 always begin if (!clk_en && clk==1'b1) begin wait (clk_en); end #5 clk = ~clk; end 

The key difference between RTL and Behavioral is its synthesis ability. This behavior if you see # delay, wait statements, while loops, force / release statements or a hierarchical link. Technically, there are some rare exception exceptions, but this is beyond the scope of this question.

Gate Level (aka Structural): Logic described only with a gate and modules. There are always blocks or assign statements. This is a representative of the real gate in the equipment.

Verilog Netlist is a collection of Verilog modules used in design. It can be one or several files. It could be a combination of RTL, Behavioral and Structural. Usually it is mostly structural, especially for large structures.

Answer 2

• Behavioral level.
• RTL level (does not have to be a goal level, but a primitive level.
• Mixed working module / testbench, all in one module. Not the best approach to design with Verilog, but it would be good for an example of training. In fact, this example is actually two modules:

Testbench, which can be considered behavioral even if it uses RTL encoding to create an instance of the module that will be tested on the registers and wires that are provided in testbench:

 module testbench_dff; wire Q,Q_BAR; reg D,CLK; // Instantiate the unit under test dff_from_nand uut (.CLK(CLK), .D(D), .Q(Q), .Q_BAR(Q_BAR) ); // Testbench initial begin $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR); CLK = 0; D = 0; #3 D = 1; #3 D = 0; #3 $finish; end always #2 CLK = ~CLK; endmodule 

Testable module under test (UUT), which is a module similar to this (which, obviously, is an RTL level -gate level-module module):

 module dff_from_nand ( input wire CLK, input wire D, output wire Q, output wire Q_BAR ); wire X,Y; nand U1 (X,D,CLK) ; nand U2 (Y,X,CLK) ; nand U3 (Q,Q_BAR,X); nand U4 (Q_BAR,Q,Y); endmodule 

I understand that an RTL level module is a module in which logical equations are an explanation. The behavioral module has processes (in Verilog using always blocks, although logical equations can be used inside these blocks). Any non-trivial Verilog design will have both.

Answer 3

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