Is it possible to use memory barriers only on the storage side

Question

Firstly, some context: I work with the original atomic model based on pre-C11, inline-asm, but for the purpose of this, I gladly ignore the C aspect (and any problems with compiler barriers that I can deal separately), and we will consider it essentially only as a matter of asm / cpu architecture.

Suppose I have a code that looks like this:

various stores barrier store flag barrier 

I want to read flag from another processor core and conclude that various stores already completed and made visible. Can this be done without any instructions on protecting the memory on the boot side? It is clear that this is possible, at least on some processor architectures, for example x86, where an explicit memory barrier is not needed for any core. But what in general? Does it really depend on cpu arch, is this possible?

Answer 1

If the CPU was supposed to reorder the loads, a load barrier would be required for your code to work correctly. There are many architectures that perform this reordering; see table in memory order for some examples.

Thus, in general, your code does indeed require load limits.

x86 is not very typical in that it provides rather stringent guarantees of memory order. See Who ordered the x86 memory fence? for discussion.