Cache Specifications for i7 i7 Core

Question

I am creating a cache simulator for the i7 core, but I can hardly find detailed specifications for the L1, L2, and L3 cache (general). I need cacheblock size, cache size, associativity, etc. Can someone point me in a good direction?

Answer 1

The Intel Optimization Guide describes most of the required specifications for each generation of architecture (you did not specify which i7 you have, there are currently several generations with Nehal and before Haswell).

Haswell, for example, would have -

Please note that if you are creating a simulator, you will want as many parameters as possible to be parameterized. There are also many other considerations that you need to consider that are explained there (e.g. for inclusion, writeback / write protocols, cache negotiation protocols, etc.).