Function and difference between $ () and $ {} in Makefile

Question

In the make file ${CC} -o myfile myfile.c and $(CC) -o myfile myfile.c both work fine even without a CC definition. My question is:

• How to use $ () and $ {}?

  • Do they just convert the string in {} or () to lowercase if that string is not defined?
  • Why $$ {dir} needs two $$ in
    for dir in ${DIR}; do (cd $${dir}; ${MAKE}); done

• Are there any differences between $ {} and $ ()?

Answer 1

The previous answer is incorrect: there is no difference between () and {} for Make.

If you use $$ in the recipe, then $ "escaped" and passed to the shell. Then the shell can make the difference between $() or ${} . But it depends entirely on the shell and has nothing to do with Make or make files.

In the recipe command that you specify

 for dir in ${DIR}; do (cd $${dir}; ${MAKE}); done 

Do it:

• replaces the DIR value, for ${DIR} , and it could also be $(DIR)
• replaces $$ with $ ("escaping", so $ can be passed to the shell)
• replaces the MAKE value for ${MAKE} , again it could be $(MAKE) . The MAKE value is automatically set using Make to the make executable that is used.
• passes the resulting string to the shell for execution - the shell then interprets the remaining ${} as it wants.

CC , like MAKE , is one of those variables that are predefined by Make, so it "works" even if you don't set it yourself.

By the way, the best way to write this recipe for "target" is

 .PHONY: $(DIR) target: $(DIR) $(DIR): $(MAKE) -C $@ 

Please refer to the manual for an explanation of strange things.

Answer 2

 $ (CC) - is evaluate;  this can be a command

 Vs

 $ {CC} - is dereference;  just get value of a variable