How to represent interruption in a UML sequence diagram?

Question

I want to create a simple embedded system . The peculiarity of this is that I want to create my architecture using UML . Among the other diagrams that I use, I have a sequence diagram as shown in the figure below.

What I'm trying to portray here is that the sequence enclosed in the “LOOP” snippet runs over and over again until there is an event.

An interrupt processing unit (ISR) in the right corner of the diagram is a block that runs asynchronously and generates the expected event.

The problem is that since the event can be generated at any time during the cycle, only once every time, for example, every 10 ms and sent to "Module 2", I do not know how this means.

If I just put the arrow with the arrows of the message from the “ISR” block into “Module 2”, I understand that this means that the message containing the event will be sent from “ISR” to “Module 2” as part of the loop, each time, when the loop executes, but that is not what I need. I need to depict the fact that a message from "ISR" to "Module 2" is sent only every X milliseconds or randomly in time (in case of a hardware interrupt).

Any suggestions?

Answer 1

The sequence diagram is intended to describe a specific implementation. To describe all the possible actions, you must use the state machine diagram.

Answer 2

I am not 100% sure, but I think that this is not possible only with sequence diagrams (I will continue to look at it ...). I would save this sequence diagram to simulate the core of the loop and use the activity diagram to model the exception. The general idea would be to simulate, as shown below, at least a CallBehavior that will call your sequence, an ExceptionHandler, to catch your exception and handle your exception, which may be different behavior or what you want. Hoping this helps,