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Verilog Flowchart Program

I want to create a program to analyze Verilog and display a flowchart. Can someone help me regarding which algorithms I need to learn? I found a good Verilog parser, but now I need to find a connection between each block and place them accordingly. It does not have to be highly optimized.

UPDATE:

I now use ironPython to draw a block diagram in Visio.

  • Create a list of blocks with their inputs and outputs
  • Create a schedule that matches all block outputs to their corresponding inputs. This basically has all the connections between the blocks.
  • Find a place for them on the Visio chart.
  • Draw them in Visio
  • Connect them to Visio.
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3 answers

Yosys is an open source verilog synthesis tool. It can also be used for structural analysis and circuit creation (using GraphViz). See screenshots on the web page:

If I understand your requirements correctly, Yosys is already doing what you want. If you still want to write your own program, you can use Yosys as a link to get started.

(Conflict of Interest Disclosure: I am the author of Yossis.)

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You can also try synthesizing Altera, EASE, HDL designer, Synplify HDL Analyst, nSchema or Xilinx PlanAhead.

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If you just want a viewer for the blocks and their relationships, you can try Graphviz. An example that you can find from another fooobar.com/questions/434217 / .... You can simply analyze the HDL design and build their relationship, and then write to text format in Graphviz syntax. Then call the program to create

If you want to implement an advanced viewer, for example, it can zoom in / out, pan, move to / from a block and choose what is another story.

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Source: https://habr.com/ru/post/950662/

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