What is the best way to tell if a bus contains one x in verilog?

Question

I have a bench that watches the tire. Some signals on the bus may be 1'bx. For various reasons, I need to know if any of the signals are on the 1'bx bus. What is the best way to check (not for synthesis - just for simulation purposes) if there are any x on the bus? I was hoping I could use the abbreviation and then use ===, but this does not seem to work. Thanks,

D

Answer 1

(^bus === 1'bX)

Bitwise on the bus, and then check if the result is X. If there is any bit X or Z, then the result will be X.

To find out which bit on the bus has an error:

 always @* begin for(integer i=0; i<$size(bus); i++) begin if(bus[i]===1'bX) $display("bus[%0d] is X",bus[i]); if(bus[i]===1'bZ) $display("bus[%0d] is Z",bus[i]); end end 

Answer 2

You can use $isunknown (introduced in IEEE Std 1800-2005):

 module tb; reg [3:0] data; initial begin #5 data = 4'b0101; #5 data = 4'b000x; #5 data = 4'b1111; #5 data = 4'b0x0x; #5 data = 4'b0x1x; #5 data = 4'bzzzz; #5 $finish; end always @(data) begin if ($isunknown(data)) $display($time, " data=%b has x's", data); end endmodule /* 10 data=000x has x's 20 data=0x0x has x's 25 data=0x1x has x's 30 data=zzzz has x's */ 

Note that this also applies to z as x .