VHDL initializes the vector (length is not a multiple of 4) in hexadecimal format

Question

For example, I have a vector whose length is 10. How to initialize it in hexadecimal format. (The synhesize tool complains about size mismatch because it considers the hexadecimal value to be a multiple of 4)

signal v : std_logic_vector (9 downto 0) := x"11A"; 

Thank you very much! Nigong

Answer 1

a possible workaround is to write a multiple of 4 bits as a hexadecimal value and add the remainder to the binary file, for example:

 signal v: std_logic_vector(9 downto 0) := "01" & X"1A"; 

Answer 2

x"11A" is a "bit string hexadecimal literal". Before VHDL-2008, they were supposed to be a multiple of 4 bits, hence the problem you are seeing. VHDL-2008 removed this restriction, so now you can write 10x"11A" . I do not know how much tool support exists in 2008.

Answer 3

As far as I know, there is no “direct” way to achieve what you are looking for. You can use the following, which is a valid VHDL.

 constant init : std_logic_vector (11 downto 0) := X"11A"; signal v : std_logic_vector (9 downto 0) := init(9 downto 0); 

Answer 4

Another variety of ugly hacking:

 constant init : natural := 16#11A#; signal v : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(init, 10)); 

Having written this, I think that this is the worst of the proposed options, but I leave it here as an opportunity!