What codes, such as CC, LD, and CC [M] are output when compiling the Linux kernel?

Question

When compiling Linux from scratch, I understand that compiled codes appear during compilation.

For example, CC file name, LD file name, CC file name [M].

What do these codes mean?

Answer 1

Different notations indicate the following

• [CC] - Compiles the C file into the selected object file. The object file contains the assembly code for archiving this .c file. Because it may also refer to parts that go beyond its scope. For example, calling another function in another .c file. The function call remains open in the object file, which is later included by the linker. therefore
• [LD] is the process of linking compiled objects together and linking function calls left by the open compiler. However, many parts are related to each other as the main part of the kernel, while some parts are not taken into account. And so you see
• [CC (M)] for those parts that are compiled as points for loading into the kernel at runtime. But which are not interconnected in the monolithic part of the core. But instead, it can be inserted when the kernel boots.

Answer 2

Let's look at a specific example and find out what it does in the 4.1 kernel, for example. IHEX .

Find what code does

Just run:

 make SHELL='sh -x' 

How it works: fooobar.com/questions/38647 / ...

If we select the output for IHEX , we find the lines:

 + echo IHEX firmware/e100/d101s_ucode.bin IHEX firmware/e100/d101s_ucode.bin + objcopy -Iihex -Obinary /home/ciro/git/kernel/src/firmware/e100/d101s_ucode.bin.ihex firmware/e100/d101s_ucode.bin 

therefore, we conclude that IHEX does a objcopy -Iihex .

Find where the code is defined

Each kernel command should be defined as follows:

 quiet_cmd_ihex = IHEX $@ cmd_ihex = $(OBJCOPY) -Iihex -Obinary $< $@ $(obj)/%: $(obj)/%.ihex $(call cmd,ihex) 

to configure details (e.g. V=1 and make -s ).

In general, you just need

 git grep 'cmd.* = CODE' 

to find the CODE .

I explained in detail how this system works: fooobar.com/questions/921548 / ...

Get a list of all codes

 make | grep -E '^ ' | sort -uk1,1 

CC and CC [M]

Defined in scripts/Makefile.build :

 quiet_cmd_cc_o_c = CC $(quiet_modtag) $@ cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< 

and [M] comes from target specific variables :

 $(real-objs-m) : quiet_modtag := [M] $(real-objs-m:.o=.i) : quiet_modtag := [M] $(real-objs-m:.o=.s) : quiet_modtag := [M] $(real-objs-m:.o=.lst): quiet_modtag := [M] $(obj-m) : quiet_modtag := [M] 

Then called through:

 $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE [...] $(call if_changed_rule,cc_o_c) define rule_cc_o_c [...] $(call echo-cmd,cc_o_c) $(cmd_cc_o_c); \ 

where if_changed_rule defined in scripts/Kbuild.include as:

 if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \ @set -e; \ $(rule_$(1))) 

and Kbuild.include included in the top-level Makefile.

LD

There are several versions, but the easiest way:

 quiet_cmd_link_o_target = LD $@ cmd_link_o_target = $(if $(strip $(obj-y)),\ $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \ $(cmd_secanalysis),\ rm -f $@ ; $(AR) rcs$(KBUILD_ARFLAGS) $@ ) $(builtin-target): $(obj-y) FORCE $(call if_changed,link_o_target) 

and in scripts/Kbuild.include :

 # Execute command if command has changed or prerequisite(s) are updated. # if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ @set -e; \ $(echo-cmd) $(cmd_$(1)); \ printf '%s\n' ' cmd_$@ := $(make-cmd)' > $(dot-target).cmd) 

Answer 3

He must show:

• CC when compiling the main part of the kernel
• CC [M] when compiling a module
• LD upon binding