A few colons and an equal sign in the makefile (explanation required)

Question

This is only a segment of the makefile. I do not quite understand what is happening.

OBJS = $(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o) $(OBJS):$(OBJ)/%.o: $(SRC)/%.cpp | print-opts $(cc-command) 

All I understand is that these lines compile .cpp files into .o after "print-opts" using "cc-command". But I do not understand semantics.

If I expand the "OBJS" macro, this line should be:

 $(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o) : $(OBJ)/%.o: $(SRC)/%.cpp | print-opts $(cc-command) 

For me, it looks like in $$ (SRCS: $ (SRC) /%. Cpp = $ (OBJ) /%. O) ', he claims that all .cpp in $ (SRC) came to .o in $ ( OBJ), but it will depend on $ (OBJ) /%. o, which depends on $ (SRC) /%. cpp. It does not make sense...

I do not understand what the equal sign means here and what the multiple colons mean.

Answer 1

Suppose you defined these three variables (and if you did not, the rule will not work very well):

 SRC = source_dir OBJ = object_dir SRCS = source_dir/foo.cpp source_dir/bar.cpp 

Now consider the purpose

 OBJS = $(SRCS:$(SRC)/%.cpp=$(OBJ)/%.o) 

This is a reference to substitution ; he says, "for something in $(SRCS) that has the form $(SRC)/%.cpp , change it to $(OBJ)/%.o ". So, OBJS will be evaluated to object_dir/foo.o object_dir/bar.o

Now the rule:

 $(OBJS):$(OBJ)/%.o: $(SRC)/%.cpp | print-opts $(cc-command) 

Thuis is a static rule of patterns . It defines a list of goals ( $(OBJS) ), a target pattern ( $(OBJ)/%.o ) and a background pattern ( $(SRC)/%.cpp ). Map the target to the target template and use this to create the name of the desired condition. So if Make Use this rule to build object_dir/foo.o , the stem will be foo , and source_dir/foo.cpp will be a source_dir/foo.cpp .

(You did not ask about | print-opts , so I assume it has already been cleared.)