The best way to encode a D trigger

Question

I recently saw some D-trigger RTL code in verilog as follows:

module d_ff( input d, input clk, input reset, input we, output q ); always @(posedge clk) begin if (~reset) begin q <= 1'b0; end else if (we) begin q <= d; end else begin q <= q; end end endmodule 

Does the statement q <= q; ?

Answer 1

Does the expression q <= q; is it necessary?

No, this is not the case, and in the case of ASIC, it can actually increase the area and power consumption. I’m not sure how modern FPGAs manage. During synthesis, the instrument will see this operator and will require q updating on each positive edge of the clock signal. Without this final else clause, the tool can only update q only if the specified conditions are met.

In ASIC, this means that the synthesis tool can insert a clock-clock (if the library has one) instead of a multiplexer. For one DFF, this can be really worse, since the clock is usually much larger than the multiplexer, but if q is 32 bits, then the savings can be very significant. Modern tools can automatically determine whether the amount of DFF matches the shared resolution with a specific threshold value, and then selects a clock valve or multiplexer accordingly.

In this case, the tool needs 3 multiplexers plus additional routing.

 always @(posedge CLK or negedge RESET) if(~RESET) COUNT <= 0; else if(INC) COUNT <= COUNT + 1; else COUNT <= COUNT; 

Here the tool uses a single timer for all DFFs.

 always @(posedge CLK or negedge RESET) if(~RESET) COUNT <= 0; else if(INC) COUNT <= COUNT + 1; 

Images here

Answer 2

Regarding modeling, deleting this statement should not change anything, since q must be of type reg (or logic in SystemVerilog) and must contain its value.

In addition, most synthesis tools should generate the same pattern in both cases, since q is updated using a non-blocking assignment. Perhaps the best code would be to use always_ff instead of always (if your tool supports it). Thus, the compiler verifies that q is always updated using a non-blocking assignment and consistent logic is generated.