Processors have a privileged register called the base page table register (PTBR), on x86 it has CR3 . When switching context, the OS changes the PTBR value so that the processor now knows which page table to use. In addition to PTBR, many modern processors have the concept of an address space number (ASN). Processes are assigned an address space number (from a restricted pool), and this ASN is also set in a register in the context switch. This ASN is used as part of the TLB mapping and allows the use of TLB entries from multiple address spaces. Only when reusing the ASN is it necessary to clear the TLB, and then only for entries matching the ASN. Most x86 implementations are rougher than this, and there is the concept of global pages (for shared libraries and shared data).
source share