What happened to this LLVM register number?

Question

I am writing a compiler for a simple C-like language for the course I am taking. This bit of code:

int main() { printInt(not(0)); return 0; } int not(int n) { if (n == 0) { return 1; } else { int result = 0; return result; } } 

.. I naively compile this bitcode:

 declare void @printInt(i32) declare void @printDouble(double) declare void @printString(i8*) declare i32 @readInt() declare double @readDouble() define i32 @main() { entry: %0 = call i32 @not(i32 0) call void @printInt(i32 %0) ret i32 0 unreachable } define i32 @not(i32 %n_0) { entry: %0 = icmp eq i32 %n_0, 0 br i1 %0, label %lab0, label %lab1 lab0: ret i32 1 br label %lab2 lab1: %result_0 = alloca i32 store i32 0, i32* %result_0 %1 = load i32* %result_0 ret i32 %1 br label %lab2 lab2: unreachable } 

However, opt does not accept this code.

 opt: core023.ll:25:5: error: instruction expected to be numbered '%2' %1 = load i32* %result_0 

Now, from what I understand about unnamed temporary registers, they should be numbered sequentially, starting with 0. What happens here. But apparently, the line "% 1 = south" should be numbered% 2. Why is this? Does any of the instructions between% 0 and% 1 execute a sequence number? Or maybe it's just a follow-up error from something else?

Answer 1

In LLVM, everything that can have a name but is not assigned a number. It also includes base units. In your case

 lab0: ret i32 1 br label %lab2 

defines two base blocks because each terminator statement ends the base block. This means that, in theory, your code is parsed as

 lab0: ret i32 1 1: br label %lab2 

and the next free number after that is 2.

To prevent strange behavior like this, I recommend always explicitly specifying base blocks.