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64-bit unreadable PCIe spaces

I read the horror, which is a PCIe specification, and still cannot get any permission for the next couple of questions.

  • Does PCIe support matching huge (e.g. 16 GB) 64-bit unreadable memory spaces above the 4 GB border? Or are they still tied to the same 1 GB as on 32-bit days, and it is simply impossible to call giant rows of non-standard space?

  • Assuming the spec allows this (and, to my reading, it does), do the widely available BIOS support it? Or is this allowed theoretically, but not done in practice?

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2 answers

TL DR / Short Answer

Not. Non-standard memory BAR requests are limited to using the lower 32-bit address space.

http://www.pcisig.com/reflector/msg03550.html

Long answer

The reason the answer is not related to internal PCI components. The data structure, which describes the memory ranges that the PCI bus includes, reserves enough space to store 32-bit base and limit addresses for non-standard memory and I / O memory ranges. However, it reserves enough space for storing a 64-bit base and limits for pre-fetching memory.

Even longer answer

In particular, see http://wiki.osdev.org/PCI#PCI_Device_Structure , Figure 3 (PCI-to-PCI Bridge). This shows the PCI Configuration Type 0x01 header (the header format for the PCI-to-PCI bridge). Please note that starting from register 1C in this table there are:

  • 1C: 8 (middle) bit for the base I / O address. Only the top 4 bits are available.
  • 1D: 8 (middle) bit for I / O address limit. Only the top 4 bits are available.
  • Ignore 1E-1F.
  • 20: 16 bits for the base address without prefetching. Only the top 12 bits are available.
  • 22: 16 bit for invalid memory limit. Only the top 12 bits are available.
  • 24: 16 (middle) bit for base prefetch address
  • 26: 16 (middle) bit for prefix memory limit
  • 28: 32 high bits for extended base prefetch address
  • 2C: 32 high bits for extended prefix memory limit
  • 30: 16 high bits for extended base I / O address
  • 32: 16 high bits for extended I / O limit address

Actual addresses are created by concatenating (parts) of these registers together with 0s (for base addresses) or 1 (for limit addresses). The base and limit I / O addresses, without prefetching, are 32-bit and are formed in this way:

Bit# 31 20 19 16 15 0 I/O Base: [ 16 upper bits : 4 middle bits : 12 zeros ] I/O Limit: [ 16 upper bits : 4 middle bits : 12 ones ] Non-prefetchable Base: [ 12 bits : 20 zeros ] Non-prefetchable Limit: [ 12 bits : 20 ones ]

Preloaded base and limit addresses are 64-bit and are formed in this way:

 Prefetchable Base: Bit# 63 32 [ 32 upper bits ] [ 12 middle bits : 20 zeros ] Bit# 31 16 15 0 Prefetchable Limit: Bit# 63 32 [ 32 upper bits ] [ 12 middle bits : 20 ones ] Bit# 31 16 15 0

As you can see, only a pre-loaded memory base and limit registers have enough bits set to express a 64-bit address. All others are limited to only 32.

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PCIe can detect 64b memory addresses. The definition and use of BARs (Base Address Registers) is defined in the PCI 3.0 specification (section 6.2.5.1 Address Cards) not in the PCIe specification.

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Source: https://habr.com/ru/post/914937/

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