Yes. There are several ways to affect performance. The standard protocol that the user uses is some version of MSI (Modified, Shared, Invalid), sometimes with O (Owner) and often E (Exclusive) added to the protocol. In your example, core A will start in the Modified (or Exceptional) state, and reading basically B will force core A to change it to Shared state. This action takes cycles in the cache, since there are only so many operations that the kernel can perform at any given time. The impact of this on Core A is not very large, as it is not in a critical way. What is more influential is what Core A writes again. Since the cache line is in general (or invalid) state, it should issue a request to upgrade to M or E. This request should go to kernel B. This operation is on a critical path, and the write cannot complete until the cache block is updated. However, records are usually buffered, and the processor is usually not blocked during this operation.
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