Verilog prints a signed integer stored in a variable of type reg

Question

How to print a signed integer value stored in an 8-bit register declared as

reg [7: 0] acc;

Using

$ display ("acc:% d", acc)

It prints an unsigned value.

What is the correct syntax for the $ display function?

Answer 1

If you declare reg as signed , $display will show a minus sign:

 module tb; reg signed [7:0] acc; initial begin acc = 8'hf0; $display("acc : %d", acc); end endmodule /* Prints out: acc : -16 */ 

Answer 2

The SystemVerilog 2012 standard also got into this problem and looked at it, but did not notice the mention of subscription in the section on format specifiers. An alternative (mostly equivalent) solution is also used here:

 $display("acc : %d", $signed(acc)) 

The $ signed function converts the input value to a signed type with the same bit width.