How many registers exist in 8086/8088?

Question

I took a course in Computer Architecture and realized that the processor has 32 registers in each of the 32 bits. Now I am studying a computer architecture course in which I read that 8086 has 8 registers only . But the book I read, and this website shows a lot of registers. I got confused in the registers in 8086 and 8088. Please help me.

Note:

I have a good understanding of different register sizes in different processors. I just got confused in the number of registers.

Answer 1

8086 and 8088 are 16-bit processors - each of them has a width of 16 bits. (In a few instructions, the combination of DX and AX is treated as a 32-bit integer, such as div input and mul output.)

Note that the 8086 has a 16-bit data bus; The 8088 has an 8-bit data bus. (Thus, loading / saving a 16-bit word takes 2 clock cycles of the bus. Addresses are still 20-bit for both.)

GENERAL PURPOSE OF REGISTRATION

The 8086 processor has 8 general-purpose registers, each of which has its own name:

AX - battery register (divided by AH / AL):

Generates shortest machine code: short-form encodings exist Arithmetic, logic and data transfer One number must be in AL or AX Multiplication & Division Input & Output 

BX - base address register (divided by BH / BL).

 Offset address relative to DS by default 

CX - account register (divided by CH / CL):

 The LOOP instruction uses it implicitly as a counter Repetitive operations on strings with the REP command Count (in CL) of bits to shift and rotate 

DX - data register (divided into DH / DL):

 DX:AX concatenated into 32-bit register for some MUL and DIV operations Specifying ports in some IN and OUT operations 

SI - source index register:

 Can be used for pointer addressing of data Used as source in some string processing instructions Offset address relative to DS by default 

DI - destination index register:

 Can be used for pointer addressing of data Used as destination in some string processing instructions as ES:DI Offset address relative to DS outside of string instructions 

BP - base pointer:

 Primarily used to access parameters and locals on the stack Offset address relative to SS 

SP - stack pointer:

 Always points to top item on the stack Offset address relative to SS (but can't be used in 16-bit addressing modes) Should always points to word (byte at even address) An empty stack will have SP = FFFEh 

SEGMENT REGISTERS

• CS - indicates a segment containing the current program.
• DS - usually indicates the segment where the variables are defined.
• ES is an optional segment register, it is up to the encoder to determine its use.
• SS - indicates a segment containing a stack.

Although you can store any data in segment registers, this is not a good idea. Segment registers have a special purpose - to indicate available blocks of memory.

Segment registers work together with a general register to access any memory value. For example, if we want to access memory at the physical address 12345h (hexadecimal), we could set DS = 1230h and SI = 0045h. Thus, we can form 20-bit linear addresses instead of 16-bit with one register. (This is applicable in real mode; in protected mode, the segmentation is different.)

The processor calculates the physical address by multiplying the segment register by 10h and adding a general purpose register (1230h * 10h + 45h = 12345h):

An address formed from 2 registers is called an effective address.
By default, the BX, SI, and DI registers work with the DS segment register;
BP and SP work with SS segment register.
Other general purpose registers cannot form an effective address.
In addition, although BX can form an effective address, BH and BL cannot.

SPECIAL REGISTRATION PURPOSES

IP - instruction pointer:

 Always points to next instruction to be executed Offset address relative to CS 

The IP register always works with the CS segment register and indicates the instruction that is being executed.

FLAG REGISTRATION

Flags Register - determines the current state of the processor. They are automatically modified by the CPU after mathematical operations, which allows you to determine the type of result and determine the conditions for transferring control to other parts of the program. Generally, you cannot access these registers directly.

 Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0. Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in (the low 8 bits of a) result, and to 0 when there is odd number of one bits. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow (carry-out) for low nibble (4 bits). Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to 0. (This flag takes the value of the most significant bit.) Trap Flag (TF) - Used for on-chip debugging. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. Direction Flag (DF) - this flag is used by some instructions to process arrays. When this flag is set to 0 the processing is done forward, when this flag is set to 1 the processing is done backward. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes 100 + 50 (result is not in range -128...127). 

Answer 2

I took a course in computer architecture, and I realized that the processor has 32 registers each of 32 bits.

This does not answer your question, but if you want to communicate with the annotator engineer, you must use the correct language. Saying that "(some) processor has 32 registers whose size is 32 bits", you will not get anywhere, there are countless processors.

In 8086 there were eight (more or less common) 16-bit registers, including the stack pointer, but excluding the instruction pointer, flag of registers and segment registers. Four of them, AX, BX, CX, DX, could also be available as twice as many 8-bit registers (see the figure), while the other four, BP, SI, DI, SP, were only 16-bit .

I guess the confusion comes from this suggestion on Wikipedia. Both sources you are reading are correct. There are 8 common purpouse registers (in an article he noted as “more or less general”, I don’t know who could write this), these are: AX BX CX DX and SI DI BP SP. There are also segment registers, special purpouse registers and a flag register (which are marked after the word "exclude", which, I assume, is read as "there are registers, there are 8 of them, if you exclude these 3 groups", this is undefined).

The problem is the wording. The above sentence is confusing, and I can see where your question comes from. This never stops asking, but you must understand that Wikipedia is not a reliable source of knowledge, if you are ever confused, just grab a book.

Answer 3

8086 has 14 16-bit registers. AX, BX, CX, DX, SI, DI, BP, SP, CS, DS, SS, ES, IP and flag register. The last two are only available indirectly.

Answer 4

Books on computer architecture often use MIPS as an example because it is pretty simple and informative. MIPS has 32 registers, but this does not mean that other 32-bit architectures also have 32 registers. 32-bit here only means that the computer has 32-bit address / 32-bit integer registers . This has nothing to do with the number of registers.

ARM, the most popular 32-bit architecture, has 16 registers (although ARMv8 64-bit doubled that number to 32). Many other 32-bit architectures also have a register number different from 32, for example, Motoroka 68k and SuperH v2 / 3/4, all 16 registers. See the list of architectures here . You see, 64-bit architectures rarely have 64 registers, as this will significantly increase the size of the register file and worsen context switching. Most of them have 32 registers.

x86, being backward compatible with 8086 many decades ago, has only 8 visible integer registers. But in fact, x86 processors currently have hundreds of registers inside and use register renaming to overcome the limitation on the number of registers.