Designing a MIPS Processor Using VHDL - Any Good Tutorials?

Question

I am confused by VHDL best practices - for example, when you need to use integer or real or a signal or std_logic_vector . I participate in a computer organizational class, and we implement it using mostly flowcharts in Quartus, with a little VHDL. The problem is that our entire project is simply scattered and error prone, and it has been painful so far.

I think VHDL would make a lot more sense, and I wrote some components, but we did not learn a lot of VHDL in the class, and google does not provide many good tutorials. I also googled for VHDL MIPS implementations / tutorials, but to no avail.

This is a vague question, but I just need a push in the right direction. Three questions I can ask now:

• How to connect all my components in VHDL (register file, apu, memory, ...)?
• When do I use integer / real / std_logic?
• I saw some VHDL code that has the specified delay until the value is output. When should I do this in datapath MIPS?

EDIT: Along with the answer already received, I would recommend http://www.fpga.com.cn/hdl/training/Vhdl_Golden_Reference_Guide.pdf , which explains everything so well. Without this tutorial, I would have to buy a book because collecting the language together by reading bits of code does not work.

Answer 1

 I also googled for VHDL MIPS processor implementations/tutorials, but to no avail 

There are quite a few MIPS cores written in VHDL in the public domain. You can look at them to get some ideas ...

• http://opencores.org/project,plasma
• http://opencores.org/project,minimips
• http://users.ece.gatech.edu/~hamblen/ALTERA/altera.htm

I have successfully used the first in several projects.

Answer 2

I am confused about VHDL best practices - for example, when to use integer or real or signal or std_logic_vector .

You cannot use real for synthesis (i.e. not for anything that ends in a real chip)

Use integer or signed or unsigned when you need to do arithmetic of values. Use std_logic[_vector] only when you need port pins that can handle high impedance. Use std_ulogic[_vector] if you need one bit or bag-bit inside. The advantage of std_ulogic is that only one can control the signal by definition, so if you make a mess and control it from two places, the compiler will tell you. Otherwise, you have a simulation full of X in the waveform viewer and don't know where they came from.

signal are used to pass values ​​between different function blocks (either entity blocks or process blocks). variable are used in processes to track things.

How to connect all my components to VHDL (register file, apu, memory, ...)?

With signals. Sigasi editor makes this a lot easier (less typed )

Do not create a component - you already have an entity , use direct instantiation:

 ALU1 : entity work.alu port map ( clk => clk, etc... ); 

VHDL code that has the specified delay until the value is displayed. when should i do this in datapath MIPS?

You do not want to specify delays - they are ignored in the synthesis, and if your design is completely synchronous (all this is a synchronized process with one hour running all over the place), the compiler will sort the real delays for you later, you can abstract above this.

Answer 3

• You connect them to signals - that is, you declare a signal, then connect the signal to the output of one component, and the input of another - it is like a wire (or many wires in the case of std_logic_vector or an integer, etc.).

• You can do everything in std_logic if you want, just as you can write all programs in assembler code. For non-synthesized VHDLs (i.e. Test benches, etc.) you can use real and integer as much as possible. For synthesized VHDL, you can use an integer and let the VHDL compiler display the base representation in terms of std_logic - if you start to do this, make sure you check the compiler output to see how it represented the integers (for example, this can use std_logic_vector (31 downto 0) for an integer than just a range from 0 to 7 - in this case, you need to help the compiler output the correct base std_logic_vector). As for real ones, it's probably best to leave non-synthesizable VHDL, and you can use floating point types in VHDL 2008 for synthesized real numbers.

• You can create Datapath MIPS without specifying any delays. If you do not know why you need it, do not use them. When you move on to synthesis, a design can have very poor temporal characteristics (i.e., it works only at a few hundred kHz) - you can go back and start pipelining the design. But, as I said, it might be best to start with a simple one and forget about the deadlines at the moment - just earn a design and synthesize it, and then start working with time material.

If you are looking for a good book on this topic, I recommend "Digital Design and Computer Architecture" by David Harris and Sarah Harris

Hope that helps