MIPS Pipeline Forwarding (Danger of Duplicate Data)

Question

In the book of Patterson and Hennessey:

But can this be treated as danger EX:

Why is the forwarding performed at the MEM stage? And How? With 1 stall (for the second addition I need the result from EX in the next EX)?

Answer 1

Document used http://www.cs.cornell.edu/courses/cs3410/2011sp/faq/faq_pa1.html

I rewrote the hazard condition EX and MEM (reducing! = 0 for simplicity) before we take into account the “double data hazard” (the original rules ):

EX Hazard

if (EX/MEM.RegWrite and (EX/MEM.RegisterRd == ID/EX.RegisterRs) # =EX_h_Rs ) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd == ID/EX.RegisterRt) # =EX_h_Rt ) ForwardB = 10 

I will call the conditions EX_h_Rs and EX_h_Rt to keep the formulas shorter

MEM Hazard (initial state)

  if (MEM/WB.RegWrite and (MEM/WB.RegisterRd == ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd == ID/EX.RegisterRt)) ForwardB = 01 

====

And our example with two types of danger at the same time, between (1st and 3rd) and (2nd and 3rd) at the same time:

 add $1, $1, $2 add $1, $1, $3 add $1, $1, $4 

or (promlem loop marked ** above and below)

  ** add C+A -> A ... A v ? add B+A -> A v add C+ A -> A ** 

According to my link, after taking into account the double danger EX + MEM: (without! = 0 and reordered Boolean terms), Updated MEM hazard rules :

Let me review the forwarding conditions for the MEM hazard to take care of the “double” data hazards

  if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRs) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd == ID/EX.RegisterRs)) ) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRt) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd == ID/EX.RegisterRt)) ) ForwardB = 01 

Or the same, using a short EX_h _ *

  if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRs) and not ( EX_h_Rs ) ) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd = ID/EX.RegisterRt) and not ( EX_h_Rt ) ) ForwardB = 01 

which means:

Try switching from MEM / WB to EX; if there is no direct input to the same input operand from the registers of the EX / MEM pipeline.

Or the same

Do not try to switch from MEM / WB to EX; if there is already a transfer of a later result from EX / MEM.

I will try to illustrate:

 add C+A -> AA' v? (forwarding to 3rd instruction) A -> A'' v? add C+A -> A 

therefore, for the third rules of the original, the teams will say that Both A' from the first team and A'' from the second team should be redirected (but the multiplexer cannot be fed from two sources at one time). And changing the hazard condition, MEM says that A' should not try to forward if there is an active forward A'' , which is later.

So, your drawing is right, 2 EX dangerous routes will be sent ; But MEM hazard redirection should not be checked if there is already an active Hazard redirect.

Answer 2

This is clearly a mistake in the 4th edition book (the brackets are not balanced, for one). It is curious that the latest edition of the book (4th edition) adds the missing closing ')', but ... ends with the wrong condition yet :

I think this would be the correct version of the conditions:

 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) Forward = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not(EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) Forward = 01