How to put a small video in spartan 3e fpga?

Using the astronomical textbook 13 http://www.cosmiac.org/tutorial_13.html and ISE 10.1, the pdf file shows how to generate the image, and you can download the project by clicking on the first .zip file. At the end of the project, he says ... Now try to transfer a small video using a similar method. Note. You must modify the Matlab file accordingly to obtain information about the pixels and reader.vhd to the video specifications used. You also need to get a video that uses only 8 colors (which can be represented by the Spartan-3E panel) in order to get a clean result.

My questions ... If I have matlab.coe files (video frames), I use one port plunger (what type of bar is in the main memory generator) to stream a small video? and how do I change the reader below?

Suppose I start with 2 frames (2 images). I want to show it back back, like a video or 1 on top of another (easier).

Remember the programming language .vhdl, Xilinx ise any version (I can upgrade), Xilinx Impact.

--------------------------------------------------------------------------------- -- File Name: reader.vhd ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reader is Port ( clk, reset : in STD_LOGIC; row : in STD_LOGIC_VECTOR (9 downto 0); col : in STD_LOGIC_VECTOR (9 downto 0); addr : out STD_LOGIC_VECTOR (15 downto 0); ennormal, enencryp : out std_logic; datain : in STD_LOGIC_VECTOR (2 downto 0); dataout : out STD_LOGIC_VECTOR (2 downto 0)); end reader; architecture Behavioral of reader is constant vtop : integer := 128; constant vbottom : integer := 351; constant htop1 : integer := 64; constant hbottom1 : integer := 287; constant htop2 : integer := 352; constant hbottom2 : integer := 575; signal addr_normal : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal addr_encryp : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); signal en_normal : std_logic := '0'; signal en_encryp : std_logic := '0'; begin ens : process (clk, reset) begin if reset = '1' then en_normal <= '0'; en_encryp <= '0'; elsif clk'event and clk='1' then if (row >= vtop) and (row <= vbottom) then if (col >= htop1) and (col <= hbottom1) then en_normal <= '1'; en_encryp <= '0'; elsif (col >= htop2) and (col <= hbottom2) then en_normal <= '0'; en_encryp <= '1'; else en_normal <= '0'; en_encryp <= '0'; end if; else en_normal <= '0'; en_encryp <= '0'; end if; end if; end process ens; c_normal: process (clk, reset) begin if reset = '1' then addr_normal <= (others => '0'); elsif clk'event and clk='1' then if en_normal = '1' then if addr_normal = 50175 then addr_normal <= (others => '0'); else addr_normal <= addr_normal + 1; end if; end if; end if; end process c_normal; c_encryp: process (clk, reset) begin if reset = '1' then addr_encryp <= (others => '0'); elsif clk'event and clk='1' then if en_encryp = '1' then if addr_encryp = 50175 then addr_encryp <= (others => '0'); else addr_encryp <= addr_encryp + 1; end if; end if; end if; end process c_encryp; addr <= addr_normal when (en_normal = '1') else addr_encryp; dataout <= datain; ennormal <= en_normal; enencryp <= en_encryp; end Behavioral; 
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You may be interested in an open graphic project: http://wiki.opengraphics.org/tiki-index.php

They also use Xilinx Spartan 3, however their Verilog code is:

 svn co svn://svn.opengraphics.org/ogp 
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Source: https://habr.com/ru/post/892692/


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