How to make make run a clean target if makefile is changed

Question

If the makefile changes, do I need to rebuild all the targets correctly?

But how to say that if, after changing the makefile, it should work make clean and then make ?

Or how to instruct make to run another command in this situation? Do I have to write a special kind of goal?

Answer 1

I believe that you want to run a clean one automatically, because you want certain goals to be rebuilt when make is called. This can be achieved by adding dependencies named FORCE to the rule whose goal you always want to build, and then defining FORCE as follows: ie no rule and no dependency.

 FORCE: 

See http://www.gnu.org/software/make/manual/make.html#Force-Targets

If you want all the files to be recompiled, you add the following to the makefile:

 %.o : %.cpp FORCE $(CXX) -c $(CXXFLAGS) $< -o $@ 

Answer 2

You can try the following:

 all: Makefile.uptodate yourMainTarget Makefile.uptodate: Makefile make clean touch Makefile.uptodate 

I'm not a make expert, so I don’t know if it was a terrible hack, but it worked in my limited tests; -)

Answer 3

Rough but effective (I can't think of anything more elegant):

 include marker marker: Makefile @touch $@ $(MAKE) clean $(MAKE)