Verilog array syntax

Question

I am new to Verilog and I have a lot of problems with this. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following does not work:

reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;

doesn't just transitionTable[0] = 10;or transitionTable[0] = 8'h10;any ideas?

(In case this is not obvious and relevant: I want to create a state machine and indicate state transitions in the array, since this seems easier than a massive case switch.)

Answer 1

When using, assignyou must declare the array as wireinstead reg.

Answer 2

- FSM, . Verilog parameter, a state next_state case/endcase.

: FSM

Answer 3

:

, , FSM, , . , FPGA-, ISE ( ) , , , . FSM , FSM.

Answer 4

, , , Verilog.

, , [MSB:LSB] [LSB:MSB]. MSB:LSB, , .

, :

reg WIDTH reg_name NUMBER;

WIDTH - "" , NUMBER - .

, :

reg [7:0] transitionTable [7:0];

, (8 = 1 ), :

initial begin
    transitionTable[0] = 8'h10;
end

Verilog from - FPGA Verilog Pong P. Chu.