Where to force xilinx ISE to use a block bar?

Question

I synthesized a small device to check the output of a block bar.

I received a message from XST:

Small RAM will be implemented on the LUT to maximize performance and save the RAM block. If you want to force its implementation on a block, use the ram_style parameter / restriction .

However, I do not know where to find this option / restriction either in ISE (11.1 in my case) or in restriction files ...

I do not want to use VHDL attributes directly in my code.

Answer 1

In the project directory you will find a file called "your-design.xst". You can add the following at the end of the list (or anywhere after "run"):

-ram_style block # ( | auto | distributed )
-rom_style block # ( | auto | distributed )

, BRAM ( LUT-).

:

-auto_bram_packing yes # ( | no )

, "#" , .

ISE,

Synthesis -> Process Properties -> HDL options

.

(BTW, SE, FPGA... ... http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2)

Answer 2

run -ram_style BLOCK .