What is the L1 / L2 cache behavior for LUT and similar?

Question

Assuming the LUT say 512KB 64-bit double types. Generally speaking, how does a processor cache a structure in L1 or L2?

For example: I am referring to the middle element, is it trying to cache the entire LUT, or only some of them - say, the middle element, and then n subsequent elements?

What algorithms does the processor use to determine what it stores in the L2 cache? Is there any strategy for looking ahead?

Note. I assume x86, but I would be interested to know how other POWER, SPARC, etc. architectures work.

Answer 1

, LUT ( ?)

, , (, std::vectors), .

, ( "-" - 64 x86), , .

, , . , .

, , ( 4 x86.)

. .

Answer 2

. , , , 128 , 128 .

CPU LRU ( , ), . ( x86, , 4k 16M.)

, , CPU - , . , , .