Port below x86 for mips32

Question

Below is a sample code for the X86 arch,

#  define INC(_lval,_lqual) \
      __asm__ __volatile__ ( \
      "lock ; incl (%0)" : /*out*/ : /*in*/"r"(&(_lval)) : "memory", "cc" )

Please help me with the equivalent MIPS32 arch.

Answer 1

This is similar to the gcc inline assembly for atomic increment. This is the gcc property for atomic increment:

__sync_fetch_and_add(&_lval, 1);

Works on x86, mips32, etc.

Answer 2

I found code that may be useful to you here . It seems to actually indicate that the built-in for gcc is not implemented for this architecture.