- .

, , , ... . . - , .
verilog.
module calc_phys_address(
phys_addr, // Output of the counter
clk, // clock Input
segment, // segment
offset // offset
);
output reg [20:0] phys_addr;
input clk;
input [15:0] segment;
input [15:0] offset;
always @(posedge clk)
phys_addr[20:0] <= {segment[15:0], 4'b0} + offset[15:0];
endmodule