VHDL operator argument type mismatch

Question

I have a very simple operator problem in VHDL. I try to compare some input with logical operators, but I get an error message ...

entity test is
 port (
  paddr              : in  std_logic_vector(15 downto 0);
  psel                : in  std_logic;
  penable              : in  std_logic;
  pwrite              : in  std_logic
 );  
end entity test;

signal wrfifo_full       : std_logic; 

process (paddr, psel, penable, pwrite, wrfifo_full) is
begin
  if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then
    dt_fifo_wr_i <= '1';
  else
    dt_fifo_wr_i <= '0';
  end if;

end of process;

Unfortunately, I get the following error message:

if (((paddr (8 downto 2) = "1000000")) and (psel and penable) and (write not (wrfifo_full))) then | ncvhdl_p: * E, OPTYMM (hdl / vhdl / test.vhd, 523 | 43): operator argument type mismatch 87 [4.3.3.2] 93 [4.3.2.2] [7.2]

Anyway sees a problem?

Hooray

Answer 1

psel, penable, pwrite and wrfifo_full are all std_logic.

In vhdl, to write the test you have, they must be logical.

, 1 .

(paddr(8 downto 2) = "1000000"     and 
 psel   = '1' and penable     ='1' and 
 pwrite = '1' and wrfifo_full = '0')

Answer 2

, std- booleans.

VHDL-2008 (??), , , , , . VHDL-2008 ( :)

, VHDL2008:

VHDL-2008

4.4