Status in std_logic

Question

I defined my condition as follows:

type state_type is (s0, s1, s2, s3);
signal state   : state_type;

Now I would like to use this status information to form another signal

signal data : std_logic_vector(3 downto 0);
signal data_plus_state : std_logic_vector(5 downto 0);

....
data_plus_state <= data & state;

Does anyone know how I can coordinate the state in std_logic_vector so that I can combine these two signals?

Thanks a lot Rob

Answer 1

Define a routine that converts state to std_logic_vector.

This routine contains a case statement, something like:

case state is
  when s0 => return <std_logic_vector value for s0>;
  when s1 => return <std_logic_vector value for s1>;
  when s2 => return <std_logic_vector value for s2>;
  when s3 => return <std_logic_vector value for s3>;
end case;

Answer 2

The subroutine and the answer to the question will work very well. If you want something in a string, you can use this.

signal state_slv : std_logic_vector(1 downto 0);

state_slv <= "00" when state = s0 else
             "01" when state = s1 else
             "10" when state = s2 else
             "11";

data_plus_state <= data & state_slv;

Greetings

Answer 3

, ( ) ( ).

, . , () . , ( ) .

type state_type is (s0, s1, s2, s3);
signal state   : state_type;
signal data : std_logic_vector(3 downto 0);
type data_plus_state_type is record
    data : std_logic_vector(3 downto 0);
    state: state_type;
end record data_plus_state_type;
signal data_plus_state : data_plus_state_type;

:

data_plus_state <= (data, state);
-- or:
data_plus_state.data <= data;
data_plus_state.state <= state;