In-process back-up cycle (VHDL)?

Question

I take a university course to study digital design using VHDL, and did some reading in a book the other day when I came across the following code snippet:

architecture abstract of computer_system is
    ...

    cpu : process is
        variable instr_reg : word;
        variable PC : natural;
        ...
    begin
        loop
            address <= PC;
            mem_read <= '1';
            wait until mem_ready;
            ...
        end loop;
    end process cpu;
end architecture abstract;

Now that I understand this, as soon as the process reaches its last statement, it will return and execute the first statement (provided that the last statement was not wait, of course). And the goal loop ... end loop;is to repeat the intermediate code indefinitely. So doesn't that make the loop redundant in this case? Does it add any additional behavior that has not yet been manifested by the process?

Answer 1

, , .