What is an efficient workflow with C? - Makefile + bash script

I am working on one of my first projects that will cover more than one C file. For my first training programs, I just wrote my code in main.cand compiled with gcc main.c -o main. It worked for me when I was studying.

Now I am working on a much larger project myself. I want to continue to compile myself (or at least manually configure it) so that I can understand the process. After reading a little, I decided to make a Makefile.

Note. I also use GTK +, so I had to look for how to add this to the compilation team.

Here's what it looks like after several studies:

main:
    gcc -Wall -g main.c -o main `pkg-config --cflags --libs gtk+-2.0`

At first, I just ran make. Then I had some problems with the fact that the error "main was updated", even if I changed the file.

So I wrote a script:

#!/bin/bash
rm main
make
./main

So, I make the changes and then run this script.

Is this a good / normal system? I want to have a scalable system, as my project will grow. I suppose I can save this script and just add dependencies to the makefile and modify the main compilation command in the makefile. Am I right?

Thanks in advance.

EDIT:

Thanks for the tip on how to fix my Makefile.

So, a typical compilation process: 1) enter make, then 2) ./mainregardless of how the project is configured or its size (provided that you have written the proper make file)?

+3
3

, main main.c. , , main.c, make, main . main clean :

main:main.c
    gcc -Wall -g main.c -o main `pkg-config --cflags --libs gtk+-2.0`

.PHONY: clean
clean:
    rm -f main

, main, : make clean

make: main is up to date. , main.c , , main. main, , -B make, Sjoerd .

+10
  • make -B make --always-make , ​​
  • , , .

:

a: a.c
        gcc -o a a.c

a , a.c , a.

+3

, make , Makefiles . , , , . :

  • Makefile , , gcc -M.
  • Makefile, automake CMake. automake, ( , ).
+3
source

Source: https://habr.com/ru/post/1762786/


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