Sugiyama Layout Algorithm Extension for a Multiple Input Block

Question

I messed around using Sugiyama directed graph layout algorithm to create good verilog chain graphs. The problem I am facing is that the layout algorithm assumes that each block (or vertex) has only one input or output edge. But in real circuits, there may be blocks that have several input and output connections that are ideally stored in a fixed order.

I was thinking of adding extra vertices for each input, but somehow handled all the vertices associated with one block as a unit - in Python, something like [ [a.in], [b.in], [c.in1, c.in2] ], where c is a block with 2 inputs. The list will be flattened when constructing connection matrices between layers.

Am I on the right track? Is there an easier way to do this? Can you point me to any resources that will help me extend the Sugiyama algorithm for working with such blocks?