Does Verilog support short circuit assessment?

Question

If I have an if statement:

if(risingEdge && cnt == 3'b111)
begin
  ...
end

Will it be checked on cnt if the raiseEdge value is incorrect?

Does it even matter inside HDL?

Answer 1

For modeling, it is undefined as to whether short-circuited expressions are evaluated or not. In the example above, this does not matter, but if you have a function call on the right side, you may run into problems with undefined side effects.

See Gotcha # 52 in "Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them" by Stuart Sutherland and Don Mills.

Answer 2

, HDL, , , . - . , SystemVerilog:

if(risingEdge && cnt++ == 3'b111)
begin
  ...
end

Verilog ( SV) - verilog, , . , .

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