Need to clarify the address bar of the processor

Question

Yesterday, when I reflected on why the OS cannot use whole 64-bit addresses for addressing? I found another interesting thing. For example, take the Intel Core 2 Duo processor.

From "4.2 Alphabetical Signal Reference" Intel Core 2 Duo E8000 Processor and E7000 Series - Technical Data Sheet I found out that it has 36 address lines and 64 data lines. The data sheet shows the address lines as A [35: 3] and the data lines as D [63: 0].

What exactly does this mean? This is my understanding (with a few unanswered questions) from above:

• Since there are 36 address lines. The total addressable memory is 2 ^ 36 = 64 GB, and each physical storage device (byte) is addressed with a 36-bit number.
• Since A [2: 0] is not mentioned. This means that MMU (the paging unit will be more specific) after translating the virtual address to a physical address (using address tables), it places only 33 most significant bits in the address lines of A [35: 3]. RAM sends all 8 possible bytes (with 3 LSBs, A [2: 0]) ie. for any request in this 8 byte range. RAM sends the same 8-byte data. correctly? I think this is done for efficiency.
• What will happen next? I mean that the MMU needs 1 byte of data, but the RAM sent 8 bytes. How will he deal with this?
• Is this address bus width 36 bits since Intel is PAE enabled?
• ( Intel® Core ™ i7 Extreme Edition).:( !

Answer 1

(BE) , 8- .

0x1, A [35: 3] BE [1] ( BE , - ).

0x3: 0x0, [35: 3] BE [3: 0].

1, 2 3.

4, PAE 36 . 64- .

5...

Answer 2

5: Core i7 3 (On Chip) ( 1) 64 .

, , 3 * 64, SSE 128- - L1 (, , 64- Chache).

.

GPR u 64- ( 64- ).

36 , , .