I am trying to write a synthesized 3D rasterizer in Verilog / SystemVerilog. The rasterizer is not a 3D rasterizer right now: it just gets six 32-bit floats for the vertex position (vertA_pos_x, vertA_pos_y, vertB_pos_x, vertB_pos_y, vertC_pos_x, vertC_pos_y) and nine 8-bit integers for coloring the vertices (vertA_color_g, vertA_color_g vertB_color_r, vertB_color_g, vertB_color_b, vertC_color_r, vertC_color_g, vertC_color_b).
Position ranges: 0.0f ~ 1.0f, 0.0f representing the top / left side of the screen, 0.5f in the middle and 1.0f bottom / right side.
Raster work would be, firstly, to calculate how many raster lines are required. Given that the framebuffer is 240 pixels tall, vertex A is the top vertex, B is the bottom left, C is the bottom right, and X is the bottom vertex (either B or C; this must be calculated), the number of raster lines is specified (vertX_pos_y - vertA_pos_y) / 240.
This part of the rasterization process is complex enough to expose my doubts, so I will stop explaining how I will continue here.
Now I want to know how to implement such “complex” logic in Verilog (it is “complex” because it is consistent and takes more than one clock cycle, which is not very pleasant for design with a hardware description language).
I use Altera Quartus, and therefore I am mainly interested in Altera solutions.
, Quartus, , "" , (vertX_pos_y - vertA_pos_y) / 240, , . , - , , , , .
, Verilog , , - . ?