GNU Make - Dependencies on Non-Programming Code

Question

The requirement for the program I am writing is that it must be able to trust the configuration file. To do this, I use several hash algorithms to generate a file hash at compile time, this creates a header with hashes as constants.

The dependencies for this are pretty straightforward, my program depends on config_hash.h, which has a goal that produces it.

The make file looks something like this:

config_hash.h:
    $(SH) genhash config/config_file.cfg > $(srcdir)/config_hash.h

$(PROGRAM): config_hash.h $(PROGRAM_DEPS)
    $(CC) ... ... ... 

I use the -M option for gcc, which is great for working with dependencies. If my title changes, my program rebuilds.

My problem is that I need to determine if the configuration file has been modified so that config_hash.h is re-created. I'm not quite sure how to explain this dependency on GNU.

I tried listing config / config_file.cfg as a dependency for config_hash.h and providing .PHONYtarget for config_file.cfg without success. Obviously, I cannot rely on the -M switch on gcc to help me here, since the configuration file is not part of any object code.

Any suggestions? Unfortunately, I cannot post most of the Makefile, otherwise I would just post it all.

Answer 1

.PHONY . . - .

Answer 2

, config/config_file.cfg config_hash.h ?

config_hash.h:config/config_file.cfg
    $(SH) genhash $< > $@

config_hash.h, config/config_file.cfg . gcc- - config_hash.h.

$@ - , , , ( , srcdir, , ./config_hash.h, ./$(srcdir)/config_hash.h). $< $^ .

, makefile,

CPPFLAGS+=-MMD -MP
all:
# etc.
config_hash.h:config/config_file.cfg
    $(SH) genhash $< > $@
%.d %.o:%.c
    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $*.o $<
%.d %.o:%.cpp
    $(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $*.o $<
-include $(wildcard *.d) /dev/null