Unlike your comments, '==' is part of Verilog, and if my memory is much worse today than usual, it should be synthesized just fine. For example, you can write something like:
module add_when_equal(clock, a, b, x, y, z);
input clock;
input [31:0] a, b, x, y;
output [31:0] z;
reg [31:0] a, b, x, y, z;
always begin: main
@(posedge clock);
if (a == b)
z <= x + y;
end
endmodule;
Verilog , (! =, <= ..). "", - x != 0 N- .