Should you remove all warnings in your Verilog or VHDL design? Why or why not?

Question

In (regular) software, I worked for companies where the gcc -Wall option is used to display all warnings. Then they need to be addressed. With the non-trivial FPGA / ASIC design in Verilog or VHDL, there are often many warnings. Should I worry about all of them? Do you have any specific techniques? My stream is mainly intended for FPGAs (in particular, Altera and Xilinx), but I assume that the same rules apply to ASIC design, perhaps moreover because of the inability to change the design after its assembly.

Update 4/29/2010: I initially thought about the synthesis and warnings of P & R (Place and Route), but the warnings about the simulation are also valid.

Answer 1

Here is my view from the ASIC world (99% Verilog, 1% VHDL).

We try to eliminate all warnings from our log files, because in general we interpret warnings as a tool that tells us that we should not expect predicted results.

Since there are many types of tools that can generate warnings (simulation / debugger / linguator / synthesis / equivalence check, etc.), I will focus on discussing warnings of the compiler simulator . p>

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