How to get rid of the sensitivity list warning when synthesizing Verilog code?

Question

I get a warning that:

One or more signals are not in the sensitivity list of the block.

always@(Address)begin
  ReadData = instructMem[Address];
end

How to get rid of this warning?

Answer 1

Verilog does not require signal names in the sensitivity list. Use the syntax @*to indicate that a block alwaysshould run whenever any of its input signals changes:

always @* begin 
    ReadData = instructMem[Address]; 
end 

Answer 2

Add InstructMem to the sensitivity list.

Answer 3

ReadData , .

assign ReadData = instructMem[Address];

Answer 4

, Mem. , ReadData = instructionMem [address] , , Mem . , , , ReadData.

Icarus, - @( ), reg [7: 0]: Mem [255: 0] → .

. Verilog , , IP- . .