Syntax for using an array of wires as input

Question

I have the following module:

module add_8bit ( output wire co,
              output wire [7:0] r,

              input wire ci,
              input wire [7:0] x,
              input wire [7:0] y );

I am trying to use it with the following code:

 wire rbit [7:0];
 wire onebit [7:0];
 wire twocomp [7:0];

 wire tco, tci;

 add_8bit t9 ( tco, twocomp, tci, rbit, onebit );

Will not compile due to last line, why?

Thank.

Answer 1

You have wire declarations back in the second code snippet. Must be:

wire [7:0] rbit;
wire [7:0] onebit;
wire [7:0] twocomp;

Answer 2

In your module definition, you declared three 8-bit ports wire:

 output wire [7:0] r,
 input  wire [7:0] x,
 input  wire [7:0] y

However, in your calling module, you declared three arrays with 1-bit widths up to 8 bits wire (see IEEE Standard for Verilog, 1364-2005, Section 4.9 "Arrays):

 wire rbit    [7:0];
 wire onebit  [7:0];
 wire twocomp [7:0];

, , .

, , , , . , , wire :

wire [7:0] rbit;
wire [7:0] onebit;
wire [7:0] twocomp;

, , , , .