Can you have the module identifier as the same module type in Verilog?

Question

for instance

module top
    debouncer debouncer(...);
endmodule

module debouncer
...
endmodule

Is it possible to instantiate a debouncer as a "debouncer" in the top module, or is it illegal?

Answer 1

Yes, for the module name instance it is possible to match the module name in Verilog, and this happens quite often when you need only one instance of the module. But you could quickly check this out for yourself by simply compiling your file with your favorite simulator. The following is the legal syntax and compilation for me:

module top;
    debouncer debouncer();
endmodule

module debouncer;
endmodule