Creating a watch failure in verilog design

Question

I am creating a chip using verilog. I have a 3-bit counter. I want that when the counter is in its 8th cycle, there should be a malfunction and then work fine. What are some possible ways to create a watch failure in Verilog design?

Answer 1

One way to enter glitches into a clock signal is to use forceit releasefrom a test site:

module tb;

reg clk;
reg [2:0] cnt;
reg reset;

always begin
    #5 clk <= 0;
    #5 clk <= 1;
end

always @(posedge clk or posedge reset) begin
    if (reset) begin
        cnt <= 0;
    end else begin
        cnt <= cnt + 1;
    end
end

always begin: inject_clk_glitch
    wait(cnt == 7);
    #1 force clk = 1;
    #1 force clk = 0;
    #1 release clk;
end

initial begin
    reset = 1;
    #20 reset = 0;
    #500 $finish;
end

endmodule

Answer 2

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