Verilog: Can you put “assign” statements in the “always” or “start / end” statements?

Question

Is this allowed?

input w;
     input [8:0]y;
     output reg [8:0]x;
     always@(w)
     begin


     //x[0] or A is never on in any next state
     assign x[0] = 0;
     assign x[1]= (y[0]&~w) | (y[5]&~w) | (y[6]&~w) | (y[7]&~w) | (y[8]&~w); //B
     assign x[2]= (y[1]&~w); //C
     assign x[3]= (y[2]&~w); //D
     assign x[4]= (y[3]&~w) | (y[4]&~w); //E
     assign x[5]= (y[0]&w) | (y[1]&w) | (y[2]&w) | (y[3]&w) | (y[4]&w); //F
     assign x[6]= (y[5]&w);
     assign x[7]= (y[6]&w);
     assign x[8]= (y[7]&w) | (y[8]&w);

     end

Answer 1

You can, it's called Procedural Continuous Assignment. It overrides the usual procedural tasks, so there is no call for them in the code you sent. I'm not sure if they are synthesized, but I never had a reason to use them anyway.

A note on the code - you are missing yfrom the list of sensitivity: for example, always @( w or y )or always @(*)safer.

Answer 2

, 9.3 IEEE Verilog (, 1364-2005), " ". assign always. , , .

, , . , - .

- always .

input w;     
input [8:0] y;
output [8:0] x;
assign x[0] = 0;     
assign x[1]= (y[0]&~w) | (y[5]&~w) | (y[6]&~w) | (y[7]&~w) | (y[8]&~w); //B     
assign x[2]= (y[1]&~w); //C     
assign x[3]= (y[2]&~w); //D     
assign x[4]= (y[3]&~w) | (y[4]&~w); //E     
assign x[5]= (y[0]&w) | (y[1]&w) | (y[2]&w) | (y[3]&w) | (y[4]&w); //F     
assign x[6]= (y[5]&w);     
assign x[7]= (y[6]&w);     
assign x[8]= (y[7]&w) | (y[8]&w);

Answer 3

- , Verilog. , . .

:

 always @(*)

.

Answer 4

, . x [] x [], . <= assign =.

Answer 5

( )

- , .

Answer 6

• : (w) ..... , , w , .. .
• pin/port, -
• . , w, , / , w ,
• - / , , , , pin/port
• , verilog " ", , .