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Effective synthesis of 4-in-1 function in Verilog

I need to implement 4-to-1 function in Veriog. The input is 4 bits, a number from 0 to 15. The output signal is one bit, 0 or 1. Each input gives a different output, and the mapping from inputs to outputs is known, but the inputs and outputs themselves are not. I want vcs to optimize the code successfully, and also let it be as short / neat as possible. My solution so far:

wire [3:0] a;
wire b;
wire [15:0] c;

assign c = 16'b0100110010111010; //for example but could be any constant
assign b = c[a];

Recognizing c is ugly, and I don't know if vcs will recognize the K-card there. Will this work just like a case case or conjunctive normal form job?

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5 answers

Are you all right. The case will also work equally well. It is just a matter of how expressive you are.

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always_comb //or "always @*" if you don't have an SV-enabled tool flow
begin 
  case(a)
  begin
    4'b0000: b = 1'b0;
    4'b0001: b = 1'b1;
    ...
    4'b1111: b = 1'b0;
    //If you don't specify a "default" clause, your synthesis tool
    //Should scream at you if you didn't specify all cases,
    //Which is a good thing (tm)
  endcase //a
end //always
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-, .:-) ( , ), , case. Synopsys DC Z-2007.03-SP.

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Source: https://habr.com/ru/post/1696664/

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