Will a non-atomic load on the same cache line as an atomic variable cause the atomic variable to crash?

Question

Given something similar on an ARMv8 processor (although this may apply to many others):

class abcxzy 
{
  // Pragma align to cacheline to ensure they exist on same line.
  unit32_t atomic_data;
  uint32_t data;

  void foo()
  {
    volatile asm (
      "   ldr w0, [address of data]\n"
      "# Do stuff with data in w0..."
      "   str w0, [address of data]\n"

      "1: ldaxr w0, [address of atomic_data]\n"
      "   add w1, w0, #0x1\n"
      "   stxr w2,w1, [address of atomic_data]\n"
      "   cbnz w2, 1b\n"
    );
  }
}

With matching clobs and such a set on the Asm inline line, so that C and Asm can joyfully coexist in the world of rainbow ponies and sunlight.

In a situation with multiple processors, all those running this code at the same time will the storage facilities datacause loss of atomic load / storage atomic_data? From what I read, ARM atomic material works on a cache line basis, but it is unclear whether a non-atomic magazine will affect an atom. I hope this is not the case (and suppose it is so ...), but I am looking to see if anyone else can confirm this.

Answer 1

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Edit:

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