Why are buffers needed for target buffers for non-listing instructions?

Question

For the MIPS Stage 5 pipeline, the branch target is known at the decoding stage, because it can be easily extracted if the branch offset is in the instruction, and you also read the registers at the decoding stage.

So, then for the pipeline out of turn you ran into a problem with instructions like "jr", which can use a register that has not yet been calculated. For such applications, explicit use for the destination buffer of the branch.

But for a command like beq, I see the need for a branch predictor, but not for the target branch, because you already know the branch offset and, of course, know the current program counter so that you can easily find the branch destination.

Are register jumps the only instructions using the target branch buffer or am I missing something?

Answer 1

A prediction is required for the sampling phase to find out which block to choose next. The instruction cache has some delay, but may be pipelined. DRAM has even more latency, but it can still have a few outstanding requests (depending on the memory controller or external cache levels). Thus, for the fetch phase, it is necessary to block the addresses of several loops before the blocks that are currently coming from memory / caching .

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