Drill bit

Question

Clock synchronization is important to reduce power. How do we indicate the gating of a watch into a chisel?

Clock synchronization is where the logic signal determines whether the clock is switched to a specific register. When a logic signal is inactive, the clock remains unchanged, unchanged. Only when activation is active does the synchronization signal switch, which, in turn, latches the inputs to the trigger.

The backend tools handle the implementation insertion of this, but they need RTL to indicate the enable signal.

Answer 1

In my experience, the backend tools make a good conclusion about the inclusion of clock pulses (i.e. 95% + of my registers in my SoC remote are time synchronized).

, , , RegEnable.

Answer 2

Chisel3 MultiClock test . , , .

import chisel3._
import chisel3.experimental.withClock

class GatedCounter extends Module {
  val io = IO(new Bundle {
    val count = Output(UInt(32.W))
  })

  val counter = RegInit(0.U(32.W))

  counter := counter + 1.U

  io.count := counter
}

class HasGatedCounter extends Module {
  val io = IO(new Bundle {
    val enable = Input(Bool())
    val count  = Output(UInt(32.W))
  })

  val clock2 = (clock.asUInt()(0) & io.enable).asClock()

  withClock(clock2) {
    val counterModule = Module(new GatedCounter)

    io.count := counterModule.io.count
  }
}

.. firrtl-, verilator - , .