How to track errors in FPGA / ASIC development using post place'n 'and / or post-synthesis modeling?

Question

I got a little confused about the usefulness of PnR post and / or post-synthesis modeling for FPGA / ASIC development. If the synthesis process or PnR completes successfully in the project stream, is it likely that the corresponding simulation message will reveal design errors? Can someone give an example?

Answer 1

In a typical post-population data stream, Synthesis and / or post-PnR simulations are not useful, and the goal should be to avoid them.

, FPGA. .

, PnR , , , , 99% , Post PnR, , , , , , .

, , PnR.

- , , , .

post PnR - , - -, . -PnR- .

Answer 2

Post-PnR , . , (SDF), IEEE 1497.

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• RTL. , -PnR , -.

• / PnR . .

• Synthesis/PnR . (LEC) , .

Answer 3

Post PnR - , " " . .

• , STA .
• reset HFNS ( High Fanout Net) CTS ( ) reset , x , .
• DFT, RTL PnR.
• x - , STA

Answer 4

PAR. , , , LEC syn- > map map- > PAR.

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, PAR back-annotated SDF. .