How to limit VHDL-2008 integer_vector?

Question

VHDL-2008 defines

type integer_vector is array (natural range <>) of integer

and it can be used to create arrays of unlimited integers simply:

signal sUnconsrainedIntA : integer_vector(0 to 1) := (others => 0);

However, how to declare an array of bounded integers, for example:

-- does not work:
-- signal sConstrainedTestIntA : integer_vector(0 to 1) range 0 to 3 := (others => 0);
-- ** Error: filetest.vhd(65): Range constraints cannot be applied to array types.
-- ** Error: filetest.vhd(65): Range expression is type Integer; expecting type std.STANDARD.INTEGER_VECTOR

-- What you can do is:
type my_int_array is array (natural range <>) of integer range 0 to 3;
signal sConstrainedIntA : my_int_array(0 to 1) := (others => 0);

Is there a way to limit integers in an array without a custom type?

Answer 1

VHDL 2008 supports general package options. You can try something like:

package foo_pkg is
    generic(l, h: integer);
    subtype my_integer is integer range l to h;
    type my_integer_vector is array(natural range <>) of my_integer;
end package foo_pkg;

package foo_pkg_m17_p39 is new work.foo_pkg
    generic map(l => -17, h => 39);

package foo_pkg_p57_p134 is new work.foo_pkg
    generic map(l => 57, h => 134);

entity foo is
    port(iv1: work.foo_pkg_m17_p39.my_integer_vector(0 to 7);
         iv2: work.foo_pkg_p57_p134.my_integer_vector(0 to 7)
     );
end entity foo;

Not very user-friendly, because you need one package instance declaration to limit integers. But this is what I found that looks like what you are asking ...

Even if it looks more complex than expected, it still allows you to factor your own code for all my_integer_vector variants.