You will not find information in the VHDL standard (IEEE Std 1076-2008) and which delta cycles will not be widely understood (there is a hint about how much you really need to know as a user of the language, abstract knowledge may suffice).
Delta loops precede VHDL. You can find links on the Internet since 1971. VHDL derives its delta cycles from the CONLAN BCL time model, where they are called steps (note that we see interactive simulation commands for the step today, see Section “The Origin of VHDL Delta Delays”, SUMIT GHOSH, Int. J. Engng Ed ., T. 20, No. 4, pp. 638-645, 2004, and CONLAN Report, R. Piloty, M. Barbacci, D. Borrione, D. Dietmeyer, F. Hill, P. Skelly, Springer-Verlag 1983) .
There is a simple reference explaining the concept in Ishiura Nagisa's dissertation on Research on Logical Modeling and Language Descriptions of Devices , where in Chapter 7, describing NES: A Model of non-deterministic behavior for equipment description languages.
7.2.2 Zero delay simulation
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